Energy-Centric Scheduling for Real-Time Systems Prof. Jan Madsen
Informatics and Mathematical Modelling
Technical University of Denmark
Richard Petersens Plads, Building 321
DK2800 Lyngby, Denmark
Energy-Centric Scheduling for Real-Time Systems Prof. Jan Madsen
Informatics and Mathematical Modelling
Technical University of Denmark
Richard Petersens Plads, Building 321
DK2800 Lyngby, Denmark
Outline
The need for low power
Design of real-time systems
Power-aware design
Towards Ambient Intelligence [Weiser]
Wireless network delivers infotainment, communication, navigation, ... anyplace, anytime, for every citizen ...
Hidden, pervasive computing. IT to background, people in the foreground, improves quality of life in non-invasive way ...
Things see, listen, feel, becomes sensitive and adaptive to people ...
Electronic Devices Support Athletes
Position &
Force
Sensors Blood
Composition
(e.g. lactate) ECG,
Blood
Pressure Multiple
Hop
BAN Wireless
Link to Coach
and Med Team Wearable
Digital
Assistant curtsies Rudy Lauwereins (MPSOC02)
Smartshirt - wearable computing
... or implants
Electronic devices for diagnostics
Smart pills – 1st generation
Smart pills – 2nd generation
Global System for Ambient Intelligence
SoC
Wearable Assistants 1/person
Multimedia, games
QoS
GPS
Global connectivity
Biometric input
Health ...
Ambient control 10 ... 100 Gops 0.1-2W IF See
Hear
Feel IF Speak
Show
Stimulate RF
Global System for Ambient Intelligence
SoC
Wearable Assistants
Multimedia, games
QoS
GPS
Global connectivity
Biometric input
Health ...
Ambient control 10 ... 100 Gops 0.1-2W RF IF IF See
Hear
Feel Speak
Show
Stimulate Ad hoc network 10 m 1 m RF T C Ambient
transducers RF T C BAN body
transducers 1000 m GSM/UMTS
basestations >100/person aura after Rudy Lauwereins (MPSOC02)
What are the properties of these Ambient Intelligence architectures
”PACKAGE in a week” ”PLATFORM” @ 100..1000 times power efficiency of today’s μP Transducer node
Ultra low energy (100Mops/mW)
Low flexibility
Ultra low cost (1$)
1..10 Mtr (small size)
Low clock frequency
DSP and RF dominated
Chip package codesign
Ultra fast hardware design Assistant node
Low energy (10..50 Mops/mW)
High flexibility
Low cost (100$)
10..100 Gops, >100 Mtr
High clock frequency
Data-intensive, dynamic tasks
Task and data concurrency
Incremental software design
Design challenge
1% 10% 80% Design impact days months system RTL/firmware chip Design cycle min
Design of real-time systems
1 3 4 2 a b c 1 2 os 3 4 mapping a b c
Principles of mapping
1 2 3 Partitioning/clustering Break processes to
increase parallelism Cluster processes to
reduce communication Allocation a b Mapping Scheduling Communication 1 3 2 a b 1 2 & 3 deadline
Power consumption
PCMOS = Pstatic + Pdynamic
Pdynamic ~ a f C Vdd2
Power minimization, lower:
switching activity
clock frequency
capacitive load
supply voltage
Power reduction
> 2000 cycles 1 cycle - N/A 190 mA 720 mA Sleep Idle Active a V1 V2 Dynamic power management (DPM)
Based on processor power modes
Intel 80200
Dynamic voltage scaling (DVS)
Frequency and supply voltage can be adjusted at run-time
Usually these are discrete values and not continuous
Power reduction: DPM
r1 r1 r1 r1 r1 r1 r1 idle r1 idle r1 idle 3 1 2 3 1 2
processes are assumed to be independent
Power reduction: DVS
a a a 2 3 mem 1 1 2 3 1 2 3 V1 V2 Power profile
Power reduction: DVS
b a b a bus Single Vdd 1 2 3 4 1 2 3 4 1 2 3 4 bus b a Dual Vdd case bus b a Ideal schedule 1 3 4 2
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