MDR is a register which has two inputs and two outputs, one with memory and another with the bus.
MDRin and MDRout control the connection to the internal bus.
And, MDRinE and MDROutE control the connection with external memory bus.
The connection of MDR is shown below : * Sumaiya Iqbal, Lecturer, CSE, BUET
Computer Architecture
Lecture – 8
ALU is combinatorial circuit that has no internal storage.
It performs arithmetic and logic operations on the two operands in to its two inputs A&B.
Here, one input, A, is the output of a MUX and other input, B, comes from bus.
The result of the ALU is stored temporarily at the register Z. * Sumaiya Iqbal, Lecturer, CSE, BUET
Sequence of operations for adding the contents of register R1 and R2, and store the result in R3 is :
R1out, Yin
R2out, SelectY, Add, Zin
Zout, R3in
All the signals in one step are activated for the duration and number of the clock cycle corresponding to that step.
Other remains inactive in that step. * Sumaiya Iqbal, Lecturer, CSE, BUET
What happens in each of these steps are as follows :
R1out, Yin
In Step 1, the output of the register R1 and input of register Y is enabled at the same time.
It causes the transfer of content R1 into Y.
R2out, SelectY, Add, Zin
The contents of the register is gated onto the bus and so, reached at the B input of the ALU. * Sumaiya Iqbal, Lecturer, CSE, BUET
At the same time, the multiplexer’s select signal is set to selectY, and the contents of Y(that is, R1) comes into the input of ALU(A).
Then, for each of the operation there is a corresponding control signal.
Here, we need Add operation, so the input at A & B of ALU is added and the sum temporarily stored into Z.
Zout, R3in
In step 3, the contents of the register Z is given onto the bus from where it is then transferred into register, R3. * Sumaiya Iqbal, Lecturer, CSE, BUET
In the previous example, another extra step 3 is required just to transfer the content of Z into R3.
This activity can not be performed in step 2, because, then at the same time, both the data of register R2 and Z will be on the bus which hampers the integrity of data.
Because, at a time, only one register’s output can be connected to the bus. * Sumaiya Iqbal, Lecturer, CSE, BUET
Here, we have assumed that there are separate control signals to specify individual ALU operations, i.e. Add, Subtract, AND, XOR etc.
Here, some degree of encoding can be done.
For example, if ALU can perform eight(8) distinct operations, then 3 signal lines are enough to specify the required operation. * Sumaiya Iqbal, Lecturer, CSE, BUET
To fetch a word of information from memory, the processor has to specify the address of the memory location where the information is stored and then request a Read operation.
This process is applied for fetching both an instruction of a program and an operand required by an instruction.
The processor passes the address into MAR and a Read signal through control lines. * Sumaiya Iqbal, Lecturer, CSE, BUET
When the requested data is retrieved from memory, it is stored in MDR.
From MDR, the data can be transferred to any other register of the processor.
* Sumaiya Iqbal, Lecturer, CSE, BUET
MDR is a register which has two inputs and two outputs, one with memory and another with the bus.
MDRin and MDRout control the connection to the internal bus.
And, MDRinE and MDROutE control the connection with external memory bus.
The connection of MDR is shown below : * Sumaiya Iqbal, Lecturer, CSE, BUET
* Sumaiya Iqbal, Lecturer, CSE, BUET MDR X X X X Internal Processor Bus Memory-bus Data lines MDRoutE MDRinE MDRin MDRout Connection and Control Signals for register MDR
During memory Read/Write operations, the timing of internal processor operations and the response of the addressed device on the memory bus must be coordinated.
The processor needs one clock cycle to complete one internal data transfer.
But the speed of operation of the addressed device varies with device to device. * Sumaiya Iqbal, Lecturer, CSE, BUET
Processor has an internal cache memory.
Reading data from cache memory(cache hit) takes one clock cycle.
But when data is not found in the cache(cache miss), the request is forwarded to the main memory.
So, when a cache miss occurs, memory read operation may introduce a delay of several clock cycle.
* Sumaiya Iqbal, Lecturer, CSE, BUET
All Read/Write operations do not necessarily include memory.
A Read or Write request may also be intended for a register in the memory-mapped I/O device.
Since such I/O operations are not cached, their accesses always take a number of clock cycles.
* Sumaiya Iqbal, Lecturer, CSE, BUET
To accommodate the variability in response time, the processor waits until it receives an indication that the requested read operation has been completed.
A control signal is used for this purpose, called Memory-Function-Complete(MFC).
The addressed device sets it to 1 to indicate that the requested data has been read and is available in on the data lines of memory bus.
* Sumaiya Iqbal, Lecturer, CSE, BUET
Example of a READ operation :
Move (R1),R2
The actions needed to execute it are :
MAR [R1]
Start a Read operation on the memory bus
Wait for the MFC response from the memory
Load MDR from the memory
R2 [MDR]
* Sumaiya Iqbal, Lecturer, CSE, BUET
Each of the above actions can be carried out in separate steps.
But some can also be combined into a single step.
Each action can be completed in one clock cycle, except the 3rd one which involved waiting for MFC signal.
Depending on the speed of the addressed device , one or more clock cycles are needed for the 3rd operation. * Sumaiya Iqbal, Lecturer, CSE, BUET
The timing diagram of a memory READ operation is explained below :
Assume that the output of the MAR is always enabled.
So, the contents of MAR is always available on the address lines of the memory bus.
Here, the processor is the bus master.
When a new address is loaded into MAR, it will appear on the memory bus at the beginning of the next clock cycle.
* Sumaiya Iqbal, Lecturer, CSE, BUET
When MAR is loaded, address is given to the address line and at the same time, a READ control signal is activated.
This signal will cause the bus interface circuit to send a read command, MR(Memory-Read), on the bus.
So, here the action 1 & 2 above are combined into a single control step.
Action 3 & 4 are also combined by activating control signal MDRoutE while waiting for MFC. * Sumaiya Iqbal, Lecturer, CSE, BUET
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